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? 2005 microchip technology inc. ds21953a-page 1 MCP4821/mcp4822 features ?12-bit resolution ? 0.2 lsb dnl (typ.) ? 2 lsb inl (typ.) ? single or dual channel ? rail-to-rail output ? spi? interface with 20 mhz clock support ? simultaneous latching of the dual dacs with l dac pin ? fast settling time of 4.5 s ? selectable unity or 2x gain output ? 2.048v internal band gap voltage reference ?50ppm/c v ref temperature coefficient ? 2.7v to 5.5v single-supply operation ? extended temperature range: -40c to +125c applications ? set point or offset trimming ? sensor calibration ? precision selectable voltage reference ? portable instrumentation (battery-powered) ? calibration of optical communication devices block diagram description the microchip technology inc. mcp482x devices are 2.7v?5.5v, low-power, low dnl, 12-bit digital-to-analog converters (dacs) with internal band gap voltage reference, optional 2x-buffered output and serial peripheral interface (spi?). the mcp482x family of dacs provide high accuracy and low noise performance for industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. the mcp482x devices are available in the extended temperature range and pdip, soic and msop packages. the mcp482x devices utilize a resistive string architecture, with its inherent advantages of low dnl error, low ratio metric temperature coefficient and fast settling time. these devices are specified over the extended temperature range. the mcp482x family includes double-buffered registers, allowing simulta- neous updates using the ldac pin. these devices also incorporate a power-on reset (por) circuit to ensure reliable power-up. package types op amps v dd av ss cs sdi sck interface logic input register a register b input dac a register register dac b string dac b string dac a output logic power-on reset v outa v outb ldac shdn output gain logic gain logic 2.048v v ref MCP4821 8-pin pdip, soic, msop 1 2 3 4 8 7 6 5 cs sck sdi v dd av ss v outa shdn ldac mcp4822 8-pin pdip, soic, msop 1 2 3 4 8 7 6 5 cs sck sdi v dd av ss v outa v outb ldac 12-bit dacs with internal v ref and spi? interface
MCP4821/mcp4822 ds21953a-page 2 ? 2005 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ............................................................................................................. 6.5v all inputs and outputs ...................av ss ? 0.3v to v dd + 0.3v current at input pins ....................................................2 ma current at supply pins ...............................................50 ma current at output pins ...............................................25 ma storage temperature .....................................-65c to +150c ambient temp. with power applied ................-55c to +125c esd protection on all pins ........... 4 kv (hbm), 400v (mm) maximum junction temperature (t j ) . .........................+150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 5v ac/dc characteristics electrical specifications: unless otherwise indicated, v dd = 5v, av ss = 0v, v ref = 2.048v, output buffer gain (g) = 2x, r l = 5 k to gnd, c l = 100 pf, t a = -40 to +85c. typical values at +25c. parameters sym min typ max units conditions power requirements input voltage v dd 2.7 ? 5.5 input current - MCP4821 input current - mcp4822 i dd ? ? 330 415 400 750 a digital inputs grounded, output unloaded, code = 0x000 hardware shutdown current i shdn ?0.3 2 a software shutdown current i shdn_sw ?3.3 6 a power-on-reset threshold v por ?2.0 ? v dc accuracy resolution n 12 ? ? bits inl error inl -12 2 12 lsb dnl (note 1) dnl -0.75 0.2 +0.75 lsb device is monotonic offset error v os -1 0.02 1 % of fsr code = 0x000h offset error temperature coefficient v os /c ? 0.16 ? ppm/c -45c to 25c ? -0.44 ? ppm/c +25c to 85c gain error g e -2 -0.10 2 % of fsr code 0xfffh, not including offset error gain error temperature coefficient g/c ? -3 ? ppm/c internal voltage reference (v ref ) nominal reference voltage v ref 2.008 2.048 2.088 v v outa when g = 1x and code = 0xfffh temperature coefficient (note 1) v ref /c ? 125 325 ppm/c -40c to 0c ? 0.25 0.65 lsb/c -40c to 0c ? 45 160 ppm/c 0c to +85c ? 0.09 0.32 lsb/c 0c to +85c output noise (v ref noise) e nref (0.1-10 hz) ? 290 ? v p-p code = 0xfffh, g = 1 output noise density e nref (1 khz) ?1.2 ?v/ hz code = 0xfffh, g = 1 e nref (10 khz) ?1.0 ?v/ hz code = 0xfffh, g = 1 1/f corner frequency f corner ? 400 ? hz note 1: by design, not production tested. 2: too small to quantify.
? 2005 microchip technology inc. ds21953a-page 3 MCP4821/mcp4822 output amplifier output swing v out ? 0.010 to v dd ? 0.040 ? accuracy is better than 1 lsb for v out = 10 mv to (v dd ? 40 mv) phase margin pm ? 66 ? slew rate sr ? 0.55 ? v/s short circuit current i sc ?15 24ma settling time t settling ? 4.5 ? s within 1/2 lsb of final value from 1/4 to 3/4 full-scale range dynamic performance dac-to-dac crosstalk ? <10 ? nv-s note 2 major code transition glitch ? 45 ? nv-s 1 lsb change around major carry (0111...1111 to 1000...0000) digital feedthrough ? <10 ? nv-s note 2 analog crosstalk ? <10 ? nv-s note 2 5v ac/dc characteris tics (continued) electrical specifications: unless otherwise indicated, v dd = 5v, av ss = 0v, v ref = 2.048v, output buffer gain (g) = 2x, r l = 5 k to gnd, c l = 100 pf, t a = -40 to +85c. typical values at +25c. parameters sym min typ max units conditions note 1: by design, not production tested. 2: too small to quantify. 3v ac/dc characteristics electrical specifications: unless otherwise indicated, v dd = 3v, av ss = 0v, v ref = 2.048v external, output buffer gain (g) = 1x, r l = 5 k to gnd, c l = 100 pf, t a = -40 to +85c. typical values at 25c parameters sym min typ max units conditions power requirements input voltage v dd 2.7 ? 5.5 input current - MCP4821 input current - mcp4822 i dd ? ? 300 415 400 750 a digital inputs grounded, output unloaded, code = 0x000 hardware shutdown current i shdn ?0.25 2 a software shutdown current i shdn_sw ?2 6 a power-on reset threshold v por ?2.0 ? v dc accuracy resolution n 12 ? ? bits inl error inl -12 3 12 lsb dnl (note 1) dnl -0.75 0.3 0.75 lsb device is monotonic offset error v os -1 0.02 1 % of fsr code 0x000h offset error temperature coefficient v os /c ? 0.5 ? ppm/c -45c to +25c ? -0.77 ? ppm/c +25c to +85c gain error g e -2 -0.15 2 % of fsr code 0xfffh, not including off- set error gain error temperature coefficient g/c ? -3 ? ppm/c note 1: by design, not production tested. 2: too small to quantify.
MCP4821/mcp4822 ds21953a-page 4 ? 2005 microchip technology inc. internal voltage reference (v ref ) nominal reference voltage v ref 2.008 2.048 2.088 v v outa when g = 1x and code = 0xfffh temperature coefficient (note 1) v ref /c ? 125 325 ppm/c -40c to 0c ? 0.25 0.65 lsb/c -40c to 0c ? 45 160 ppm/c 0c to +85c ? 0.09 0.32 lsb/c 0c to +85c output noise (v ref noise) e nref (0.1-10 hz) ? 290 ? v p-p code = 0xfffh, g = 1 output noise density e nref (1 khz) ?1.2 ?v/ hz code = 0xfffh, g = 1 e nref (10 khz) ?1.0 ?v/ hz code = 0xfffh, g = 1 1/f corner frequency f corner ? 400 ? hz output amplifier output swing v out ? 0.010 to v dd ? 0.040 ? accuracy is better than 1 lsb for v out = 10 mv to (v dd ? 40 mv) phase margin pm ? 66 ? slew rate sr ? 0.55 ? v/s short circuit current i sc ?14 24 ma settling time t settling ? 4.5 ? s within 1/2 lsb of final value from 1/4 to 3/4 full-scale range dynamic performance dac-to-dac crosstalk ? <10 ? nv-s note 2 major code transition glitch ? 45 ? nv-s 1 lsb change around major carry ( 0111...1111 to 1000...0000 ) digital feedthrough ? <10 ? nv-s note 2 analog crosstalk ? <10 ? nv-s note 2 3v ac/dc characteris tics (continued) electrical specifications: unless otherwise indicated, v dd = 3v, av ss = 0v, v ref = 2.048v external, output buffer gain (g) = 1x, r l = 5 k to gnd, c l = 100 pf, t a = -40 to +85c. typical values at 25c parameters sym min typ max units conditions note 1: by design, not production tested. 2: too small to quantify. 5v extended tempe rature specifications electrical specifications: unless otherwise indicated, v dd = 5v, av ss = 0v, v ref = 2.048v, output buffer gain (g) = 2x, r l = 5 k to gnd, c l = 100 pf. typical values at +125c by characterization or simulation. parameters sym min typ max units conditions power requirements input voltage v dd 2.7 ? 5.5 input current - MCP4821 input current - mcp4822 i dd ? ? 350 440 ? a digital inputs grounded, output unloaded, code = 0x000 hardware shutdown current i shdn ?1.5? a software shutdown current i shdn_sw ?5?a power-on reset threshold v por ?1.85? v dc accuracy resolution n 12 ? ? bits inl error inl ? 4 ? lsb note 1: by design, not production tested. 2: too small to quantify.
? 2005 microchip technology inc. ds21953a-page 5 MCP4821/mcp4822 dnl (note 1) dnl ? 0.25 ? lsb device is monotonic offset error v os ? 0.02 ? % of fsr code 0x000h offset error temperature coefficient v os /c ? -5 ? ppm/c +25c to +125c gain error g e ? -0.10 ? % of fsr code 0xfffh, not including offset error gain error temperature coefficient g/c ? -3 ? ppm/c internal voltage reference (v ref ) nominal reference voltage v ref ? 2.048 ? v v outa when g = 1x and code = 0xfffh temperature coefficient (note 1) v ref /c ? 125 ? ppm/c -40c to 0c ? 0.25 ? lsb/c -40c to 0c ? 45 ? ppm/c 0c to +85c ? 0.09 ? lsb/c 0c to +85c output noise (v ref noise) e nref (0.1 - 10 hz) ? 290 ? v p-p code = 0xfffh, g = 1 output noise density e nref (1 khz) ?1.2?v/ hz code = 0xfffh, g = 1 e nref (10 khz) ?1.0?v/ hz code = 0xfffh, g = 1 1/f corner frequency f corner ? 400 ? hz output amplifier output swing v out ? 0.010 to v dd ? 0.040 ? accuracy is better than 1 lsb for v out = 10 mv to (v dd ? 40 mv) phase margin pm ? 66 ? slew rate sr ? 0.55 ? v/s short circuit current i sc ?17? ma settling time t settling ? 4.5 ? s within 1/2 lsb of final value from 1/4 to 3/4 full-scale range dynamic performance dac-to-dac crosstalk ? <10 ? nv-s note 2 major code transition glitch ? 45 ? nv-s 1 lsb change around major carry ( 0111...1111 to 1000...0000 ) digital feedthrough ? <10 ? nv-s note 2 analog crosstalk ? <10 ? nv-s note 2 5v extended temp erature specificat ions (continued) electrical specifications: unless otherwise indicated, v dd = 5v, av ss = 0v, v ref = 2.048v, output buffer gain (g) = 2x, r l = 5 k to gnd, c l = 100 pf. typical values at +125c by characterization or simulation. parameters sym min typ max units conditions note 1: by design, not production tested. 2: too small to quantify.
MCP4821/mcp4822 ds21953a-page 6 ? 2005 microchip technology inc. ac characteristics (spi? timing specifications) figure 1-1: spi? input timing. electrical specifications: unless otherwise indicated, v dd = 2.7v ? 5.5v, t a = -40 to +125c. typical values are at +25c. parameters sym min typ max units conditions schmitt trigger high-level input voltage (all digital input pins) v ih 0.7 v dd ??v schmitt trigger low-level input voltage (all digital input pins) v il ??0.2v dd v hysteresis of schmitt trigger inputs v hys ?0.05v dd ? input leakage current i leakage -1 ? 1 a shdn = ldac = cs = sdi = sck + v ref = v dd or av ss digital pin capacitance (all inputs/outputs) c in , c out ?10?pfv dd = 5.0v, t a = +25c, f clk = 1 mhz (note 1) clock frequency f clk ??20mhzt a = +25c (note 1) clock high time t hi 15 ? ? ns note 1 clock low time t lo 15 ? ? ns note 1 cs fall to first rising clk edge t cssr 40 ? ? ns applies only when cs falls with clk high. (note 1) data input setup time t su 15 ? ? ns note 1 data input hold time t hd 10 ? ? ns note 1 sck rise to cs rise hold time t chs 15 ? ? ns note 1 cs high time t csh 15 ? ? ns note 1 ldac pulse width t ld 100 ? ? ns note 1 ldac setup time t ls 40 ? ? ns note 1 sck idle time before cs fall t idle 40 ? ? ns note 1 note 1: by design and characterization, not production tested. cs sck si ldac t cssr t hd t su t lo t csh t chs lsb in msb in t idle mode 1,1 mode 0,0 t hi t ld t ls
? 2005 microchip technology inc. ds21953a-page 7 MCP4821/mcp4822 temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, av ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ?163?c/w thermal resistance, 8l-msop ja ?206?c/w note 1: the mcp482x family of dacs operate over this extended temperature range, but with reduced performance. operation in this range must not cause t j to exceed the maximum junction temperature of +150c.
MCP4821/mcp4822 ds21953a-page 8 ? 2005 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-1: dnl vs. code. figure 2-2: dnl vs. code and ambient temperature. figure 2-3: absolute dnl vs. ambient temperature. figure 2-4: inl vs. code and ambient temperature. figure 2-5: absolute inl vs. ambient temperature. figure 2-6: inl vs. code. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 1024 2048 3072 4096 code (decimal) dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 1024 2048 3072 4096 code (decimal) dnl (lsb) 125c 85c 25c 0.075 0.0752 0.0754 0.0756 0.0758 0.076 0.0762 0.0764 0.0766 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) absolute dnl (lsb) note: single device graph for illustration of 64 code effect. -5 -4 -3 -2 -1 0 1 2 3 4 5 0 1024 2048 3072 4096 code (decimal) inl (lsb) 125c 85 25 ambient temperature 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) absolute inl (lsb) -6 -4 -2 0 2 0 1024 2048 3072 4096 code (decimal) inl (lsb)
? 2005 microchip technology inc. ds21953a-page 9 MCP4821/mcp4822 note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-7: full-scale v outa w/g = 1 (v ref ) vs. ambient temperature and v dd . figure 2-8: full-scale v outa w/g = 2 (2v ref ) vs.ambient temperature and v dd . figure 2-9: output noise voltage density (v ref noise density w/g = 1) vs. frequency. figure 2-10: output noise voltage (v ref noise voltage w/g = 1) vs. bandwidth. 2.040 2.041 2.042 2.043 2.044 2.045 2.046 2.047 2.048 2.049 2.050 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) full scale v out (v) v dd : 4v v dd : 3v v dd : 2.7v 4.076 4.080 4.084 4.088 4.092 4.096 4.100 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) full scale v out (v) v dd : 5.5v v dd : 5v 1.e-07 1.e-06 1.e-05 1.e-04 1e-1 1e+0 1e+1 1e+2 1e+3 1e+4 1e+5 frequency (hz) output noise voltage density (v/ ? hz) 0.1 1 10 100 1k 10k 100k 100 10 1 0.1 1.e-05 1.e-04 1.e-03 1.e-02 1e+2 1e+3 1e+4 1e+5 1e+6 bandwidth (hz) output noise voltage (mv) 100 1k 10k 100k 1m e ni (in v rms ) 10.0 1.00 0.10 0.01 e ni (in v p-p ) maximum measurement time = 10s
MCP4821/mcp4822 ds21953a-page 10 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-11: MCP4821 i dd vs. ambient temperature and v dd . figure 2-12: MCP4821 i dd histogram (v dd = 2.7v). figure 2-13: MCP4821 i dd histogram (v dd = 5.0v). figure 2-14: mcp4822 i dd vs. ambient temperature and v dd . figure 2-15: mcp4822 i dd histogram (v dd = 2.7v). figure 2-16: mcp4822 i dd histogram (v dd = 5.0v). 180 200 220 240 260 280 300 320 340 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) i dd (a) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 0 2 4 6 8 10 12 14 16 18 20 265 270 275 280 285 290 295 300 305 310 315 320 >320 i dd (a) occurrence 0 2 4 6 8 10 12 14 16 18 285 290 295 300 305 310 315 320 325 330 335 340 345 350 >350 i dd (a) occurrence 300 350 400 450 500 550 600 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) i dd (a) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 0 5 10 15 20 25 380 385 390 395 400 405 410 415 420 425 430 435 440 i dd (a) occurrence 0 2 4 6 8 10 12 14 16 18 20 22 385 390 395 400 405 410 415 420 425 430 435 i dd (a) occurrence
? 2005 microchip technology inc. ds21953a-page 11 MCP4821/mcp4822 note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-17: hardware shutdown current vs. ambient temperature and v dd . figure 2-18: software shutdown current vs. ambient temperature and v dd . figure 2-19: offset error vs. ambient temperature and v dd . figure 2-20: gain error vs. ambient temperature and v dd . figure 2-21: v in high threshold vs. ambient temperature and v dd . figure 2-22: v in low threshold vs. ambient temperature and v dd . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) i shdn (a) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 1 1.5 2 2.5 3 3.5 4 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) i shdn_sw (a) v dd 5.5v 4.0v 5.0v 3.0v 2.7v -0.03 -0.01 0.01 0.03 0.05 0.07 0.09 0.11 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) offset error (%) v dd 5.5v 4.0 v 5.0v 3.0v 2.7v -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) gain error (%) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 1 1.5 2 2.5 3 3.5 4 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) v in hi threshold (v) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) v in low threshold (v) v dd 5.5v 4.0v 5.0v 3.0v 2.7v
MCP4821/mcp4822 ds21953a-page 12 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-23: input hysteresis vs. ambient temperature and v dd . figure 2-24: v out high limit vs. ambient temperature and v dd . figure 2-25: v out low limit vs. ambient temperature and v dd . figure 2-26: i out high short vs. ambient temperature and v dd . figure 2-27: i out vs. v out . gain = 2. 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) v in _ spi hysteresis (v) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 0.015 0.017 0.019 0.021 0.023 0.025 0.027 0.029 0.031 0.033 0.035 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) v out_hi limit (v dd -y)(v) v dd 4.0 v 3.0v 2.7v 0.0010 0.0012 0.0014 0.0016 0.0018 0.0020 0.0022 0.0024 0.0026 0.0028 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) v out_low limit (y-av ss )(v) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 10 11 12 13 14 15 16 -40 -20 0 20 40 60 80 100 120 ambient temperature (oc) i out_hi_shorted (ma) v dd 5.5v 4.0v 5.0v 3.0v 2.7v 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0246810121416 i out (ma) v out (v) v ref = 4.096v output shorted to v ss output shorted to v dd
? 2005 microchip technology inc. ds21953a-page 13 MCP4821/mcp4822 note: unless otherwise indicated, t a = +25c, v dd = 5v, av ss = 0v, v ref = 2.048v, gain = 2, r l = 5 k , c l = 100 pf. figure 2-28: v out rise time 100%. figure 2-29: v out fall time. figure 2-30: v out rise time 50%. figure 2-31: v out rise time 25% - 75%. figure 2-32: v out rise time exit shutdown. figure 2-33: psrr vs. frequency. v out sck ldac time (1 s/div) v out sck ldac time (1 s/div) v out sck ldac time (1 s/div) time (1 s/div) v out ldac time (1 s/div) v out sck ldac ripple rejection (db) frequency (hz)
MCP4821/mcp4822 ds21953a-page 14 ? 2005 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 positive power supply input (v dd ) v dd is the positive power supply input. the input power supply is relative to av ss and can range from 2.7v to 5.5v. a decoupling capacitor on v dd is recommended to achieve maximum performance. 3.2 chip select (cs ) cs is the chip select input, which requires an active-low signal to enable serial clock and data functions. 3.3 serial clock input (sck) sck is the spi compatible serial clock input. 3.4 serial data input (sdi) sdi is the spi compatible serial data input. 3.5 latch dac input (ldac ) ldac (the latch dac synchronization input) transfers the input latch registers to the dac registers (output latches) when low. can also be tied low if transfer on the rising edge of cs is desired. 3.6 hardware shutdown input (shdn ) shdn is the hardware shutdown input that requires an active-low input signal to configure the dacs in their low-power standby mode. 3.7 dac x outputs (v outa , v outb ) v outa and v outb are dac outputs. the dac output amplifier drives these pins with a range of av ss to v dd . 3.8 analog ground (av ss ) av ss is the analog ground pin. MCP4821 pin no. mcp4822 pin no. symbol function 11v dd positive power supply input (2.7v to 5.5v) 22 cs chip select input 3 3 sck serial clock input 4 4 sdi serial data input 55ldac synchronization input used to transfer dac settings from serial latches to output latches 6 ? shdn hardware shutdown input ?6v outb dac b output 77av ss analog ground 88v outa dac a output
? 2005 microchip technology inc. ds21953a-page 15 MCP4821/mcp4822 4.0 general overview the mcp482x devices are voltage-output string dacs. these devices include rail-to-rail output amplifiers, internal voltage reference, shutdown and reset-man- agement circuitry. serial communication conforms to the spi protocol. the mcp482x devices operate from 2.7v to 5.5v supplies. the coding of these devices is straight binary, with the ideal output voltage given by equation 4-1, where g is the selected gain (1x or 2x), d n represents the digital input value and n represents the number of bits of resolution (n = 12). equation 4-1: lsb size 1 lsb is the ideal voltage difference between two successive codes. table 4-1 illustrates how to calculate lsb. 4.0.1 inl accuracy inl error for these devices is the maximum deviation between an actual code transition point and its corre- sponding ideal transition point once offset and gain errors have been removed. these endpoints are from 0x000 to 0xfff. refer to figure 4-1. positive inl represents transition(s) later than ideal. negative inl represents transition(s) earlier than ideal. figure 4-1: inl accuracy. 4.0.2 dnl accuracy dnl error is the measure of variations in code widths from the ideal code width. a dnl error of zero would imply that every code is exactly 1 lsb wide. figure 4-2: dnl accuracy. 4.0.3 offset error offset error is the deviation from zero voltage output when the digital input code is zero. 4.0.4 gain error gain error is the deviation from the ideal output, v ref ? 1 lsb, excluding the effects of offset error. table 4-1: lsb sizes device gain lsb size mcp482x 1x 2.048v/4096 mcp482x 2x 4.096v/4096 v out 2.048v g d n ?? 2 n -------------------------------------- = 111 110 101 100 011 010 001 000 digital input code actual transfer function inl < 0 ideal transfer function inl < 0 dac output 111 110 101 100 011 010 001 000 digital input code actual transfer function ideal transfer function narrow code < 1 lsb dac output wide code > 1 lsb
MCP4821/mcp4822 ds21953a-page 16 ? 2005 microchip technology inc. 4.1 circuit descriptions 4.1.1 output amplifiers the dacs? outputs are buffered with a low-power, precision cmos amplifier. this amplifier provides low offset voltage and low noise. the output stage enables the device to operate with output voltages close to the power supply rails. refer to section 1.0 ?electrical characteristics? for range and load conditions. in addition to resistive load-driving capability, the ampli- fier will also drive high capacitive loads without oscilla- tion. the amplifiers? strong outputs allow v out to be used as a programmable voltage reference in a system. 4.1.1.1 programmable gain block the rail-to-rail output amplifier has configurable gain, allowing optimal full-scale outputs for differing voltage reference inputs. the output amplifier gain has two selections, a gain of 1 v/v (ga = 1 ) or a gain of 2 v/v (ga = 0 ). the output range is ideally 0.000v to 4095/4096 * 2.048v when g = 1 , and 0.000 to 4095/4096 * 4.096v when g = 2 . the default value for this bit is a gain of 2, yielding an ideal full-scale output of 0.000v to 4.096v due to the internal 2.048v v ref . note that the near rail- to-rail cmos output buffer?s ability to approach av ss and v dd establish practical range limitations. the output swing specification in section 1.0 ?electrical characteristics? defines the range for a given load condition. 4.1.2 voltage reference the mcp482x devices utilize internal 2.048v voltage reference. the voltage reference has low temperature coefficient and low noise characteristics. refer to section 1.0 ?electrical characteristics? for the voltage reference specifications. 4.1.3 power-on reset circuit the power-on reset (por) circuit ensures that the dacs power-up with shdn = 0 (high-impedance). the devices will continue to have a high-impedance output until a valid write command is performed to either of the dac registers and the ldac pin meets the input low threshold. if the power supply voltage is less than the por threshold (v por = 2.0v, typical), the dacs will be held in their reset state. they will remain in that state until v dd > v por and a subsequent write command is received. figure 4-3 shows a typical power supply transient pulse and the duration required to cause a reset to occur, as well as the relationship between the duration and trip voltage. a 0.1 f decoupling capacitor, mounted as close as possible to the v dd pin, provides additional transient immunity. figure 4-3: typical transient response. 4.1.4 shutdown mode shutdown mode can be entered by using either hard- ware or software commands. the hardware pin (shdn ) is only available on the MCP4821. during shutdown mode, the supply current is isolated from most of the internal circuitry. the serial interface remains active, thus allowing a write command to bring the device out of shutdown mode. when the out- put amplifiers are shut down, the feedback resistance (typically 500 k ) produces a high-impedance path to av ss . the device will remain in shutdown mode until the shdn pin is brought high and a write command with s d = 1 is latched into the device. when a dac is changed from shutdown to active mode, the output settling time takes < 10 s, but greater than the standard active mode settling time (4.5 s). transients above the curve will cause a reset transients below the curve will not cause a reset 5v time supply voltages transient duration v por v dd - v por t a = +25c transient duration (s) 10 8 6 4 2 0 12345 v dd ? v por (v)
? 2005 microchip technology inc. ds21953a-page 17 MCP4821/mcp4822 5.0 serial interface 5.1 overview the mcp482x family is designed to interface directly with the spi port, available on many microcontrollers, and supports mode 0,0 and mode 1,1. commands and data are sent to the device via the sdi pin, with data being clocked-in on the rising edge of sck. the communications are unidirectional and, thus, data cannot be read out of the mcp482x devices. the cs pin must be held low for the duration of a write com- mand. the write command consists of 16 bits and is used to configure the dac?s control and data latches. register 5-1 details the input registers used to configure and load the dac a and dac b registers. refer to figure 1-1 and the ac electrical characteristics tables for detailed input and output tim- ing specifications for both mode 0,0 and mode 1,1 operation. 5.2 write command the write command is initiated by driving the cs pin low, followed by clocking the four configuration bits and the 12 data bits into the sdi pin on the rising edge of sck. the c s pin is then raised, causing the data to be latched into the selected dac?s input registers. the mcp482x devices utilize a double-buffered latch struc- ture to allow both dac a ?s and dac b ?s outputs to be synchronized with the ldac pin, if desired. upon the ldac pin achieving a low state, the values held in the dac?s input registers are transferred into the dacs? output registers. the outputs will transition to the value and held in the dac x register. all writes to the mcp482x devices are 16-bit words. any clocks past 16 will be ignored. the most signifi- cant four bits are configuration bits. the remaining 12 bits are data bits. no data can be transferred into the device with cs high. this transfer will only occur if 16 clocks have been transferred into the device. if the rising edge of cs occurs prior, shifting of data into the input registers will be aborted. register 5-1: write command register bit 15 a /b: dac a or dac b select bit 1 = write to dac b 0 = write to dac a bit 14 ? don?t care bit 13 ga : output gain select bit 1 =1x (v out = v ref * d/4096) 0 =2x (v out = 2 * v ref * d/4096) bit 12 shdn : output power-down control bit 1 = output power-down control bit 0 = output buffer disabled, output is high-impedance bit 11-0 d11:d0: dac data bits 12-bit number ?d? which sets the output value. contains a value between 0 and 4095. upper half: w-x w-x w-x w-0 w-x w-x w-x w-x a /b ? ga shdn d11 d10 d9 d8 bit 15 bit 8 lower half: w-x w-x w-x w-x w-x w-x w-x w-x d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 0 legend r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
MCP4821/mcp4822 ds21953a-page 18 ? 2005 microchip technology inc. figure 5-1: write command. sdi sck cs 0 2 1 a /b ? ga shdn d11 d10 config bits 12 data bits ldac 3 4 d9 5 6 7 d8 d7 d6 8 9 10 12 d5 d4 d3 d2 d1 d0 11 13 14 15 v out (mode 1,1) (mode 0,0)
? 2005 microchip technology inc. ds21953a-page 19 MCP4821/mcp4822 6.0 typical applications the mcp482x devices are general purpose dacs intended to be used in applications where a precision, low-power dac with moderate bandwidth and internal voltage reference is required. applications generally suited for the mcp482x devices include: ? set point or offset trimming ? sensor calibration ? precision selectable voltage reference ? portable instrumentation (battery-powered) ? calibration of optical communication devices 6.1 digital interface the mcp482x devices utilize a 3-wire synchronous serial protocol to transfer the dacs? setup and output values from the digital source. the serial protocol can be interfaced to spi? or microwire peripherals com- mon on many microcontroller units (mcus), including microchip?s picmicro ? mcus and dspic ? dsc family of mcus. in addition to the three serial connections (cs , sck and sdi), the ldac signal synchronizes when the serial settings are latched into the dac?s output from the serial input latch. figure 6-1 illustrates the required connections. note that ldac is active-low. if desired, this input can be tied low to reduce the required connections from 4 to 3. write commands will be latched directly into the output latch when a valid 16 clock transmission has been received and cs has been raised. 6.2 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise. the noise can be induced onto the power supply's traces or as a result of changes on the dac's output. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 6-1 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close to the device power pin (v dd ) as possible (within 4mm). the power source supplying these devices should be as clean as possible. if the application circuit has sep- arate digital and analog power supplies, av dd and av ss should reside on the analog plane. 6.3 output noise considerations the voltage noise density (in v/ hz) is illustrated in figure 2-9. this noise appears at v outx , and is prima- rily a result of the internal reference voltage. its 1/f corner (f corner ) is approximately 400 hz. figure 2-10 illustrates the voltage noise (in mv rms or mv p-p ). a small bypass capacitor on v outx is an effective method to produce a single-pole low-pass filter (lpf) that will reduce this noise. for instance, a bypass capacitor sized to produce a 1 khz lpf would result in an e nref of about 100 v rms . this would be necessary when trying to achieve the low dnl performance (at g = 1) that the mcp482x devices are capable of. the tested range for stability is .001f thru 4.7 f. figure 6-1: typical connection diagram. 6.4 layout considerations inductively-coupled ac transients and digital switching noise can degrade the output signal integrity, potentially masking the mcp482x family?s performance. careful board layout will minimize these effects and increase the signal-to-noise ratio (snr). bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the mcp482x devices are capable of providing. particularly harsh environments may require shielding of critical signals. breadboards and wire-wrapped boards are not recommended if low noise is desired. mcp482x v dd v dd v dd av ss av ss av ss v outa v outb mcp482x 0.1 f picmicro ? microcontroller 0.1 f 0.1 f v outa v outb sdi sdi cs 1 sdo sck ldac cs 0 1f 1f
MCP4821/mcp4822 ds21953a-page 20 ? 2005 microchip technology inc. 6.5 single-supply operation the mcp482x devices are rail-to-rail (r-r) input and output dacs designed to operate with a v dd range of 2.7v to 5.5v. its output amplifier is robust enough to drive common, small-signal loads directly, thus eliminat- ing the cost and size of an external buffer for most applications. 6.5.1 dc set point or calibration a common application for a dac with the mcp482x family?s performance is a digitally-controlled set point and/or calibration of variable parameters, such as sen- sor offset or slope. 12-bit resolution provides 4096 out- put steps. if g = 1 is selected, then the internal 2.048 v ref would produce 500 v of resolution. if g = 2 is selected, the internal 2.048 v ref would produce 1 mv of resolution. 6.5.1.1 decreasing the output step size if the application is calibrating the threshold of a diode, transistor or resistor tied to av ss , a threshold range of 0.8v may be desired to provide 200 v resolution. two common methods to achieve a 0.8v range is to either reduce v ref to 0.82v (would require mcp492x device and external voltage reference) or use a voltage divider on the dac?s output. typically, when using a low- voltage v ref , the noise floor causes snr error that is intolerable. the voltage divider method provides some advantages when v ref needs to be very low or when the desired output voltage is not available. using two resistors to scale the output range down to the precise desired level is a simple, low-cost method to achieve very small step sizes. example 6-1 illustrates this concept. note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. the mcp482x family?s low 0.75 (max.) dnl performance is critical to meeting calibration accuracy in production. example 6-1: set point or threshold calibration. mcp482x v dd spi? 3 v trip r 1 r 2 0.1 uf comparator g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) v out 2.048 g d 2 12 -------- - ? = v cc + v cc ? v out v trip v out r 2 r 1 r 2 + -------------------- ?? ?? ?? = v dd r sense
? 2005 microchip technology inc. ds21953a-page 21 MCP4821/mcp4822 6.5.1.2 building a ?window? dac when calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the dac. if the lsb size is adequate to meet the appli- cation?s accuracy needs, the resolution is sacrificed without consequences. if greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. if the threshold is not near v ref , 2v ref or av ss , then creating a ?window? around the threshold has several advantages. one simple method to create this ?window? is to use a voltage divider network with a pull- up and pull-down resistor. example 6-2 and example 6-4 illustrates this concept. the mcp482x family?s low 0.75 (max.) dnl performance is critical to meet calibration accuracy in production. example 6-2: single-supply ?window? dac. mcp482x v dd spi? 3 v trip r 1 r 2 0.1 f comparator r 3 v cc- g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) v cc+ v cc+ v cc- v out v out 2.048 g d 2 12 ------- ? = r 23 r 2 r 3 r 2 r 3 + ------------------ = v 23 v cc+ r 2 () v cc- r 3 () + r 2 r 3 + ----------------------------------------------------- - = v trip v out r 23 v 23 r 1 + r 2 r 23 + ------------------------------------------- - = r 1 r 23 v 23 v out v o thevenin equivalent r sense
MCP4821/mcp4822 ds21953a-page 22 ? 2005 microchip technology inc. 6.6 bipolar operation bipolar operation is achievable using the mcp482x devices by using an external operational amplifier (op amp). this configuration is desirable due to the wide variety and availability of op amps. this allows a gen- eral purpose dac, with its cost and availability advan- tages, to meet almost any desired output voltage range, power and noise performance. example 6-3 illustrates a simple bipolar voltage source configuration. r 1 and r 2 allow the gain to be selected, while r 3 and r 4 shift the dac's output to a selected offset. note that r4 can be tied to v dd , instead of av ss , if a higher offset is desired. note that a pull-up to v dd could be used, instead of r 4 or in addition to r 4 , if a higher offset is desired. example 6-3: digitally-controlled bipolar voltage source. 6.6.1 design a bipolar dac using example 6-3 an output step magnitude of 1 mv, with an output range of 2.05v, is desired for a particular application. 1. calculate the range: +2.05v ? (-2.05v) = 4.1v. 2. calculate the resolution needed: 4.1v/1 mv = 4100 since 2 12 = 4096, 12-bit resolution is desired. 3. the amplifier gain (r 2 /r 1 ), multiplied by full- scale v out (4.096v), must be equal to the desired minimum output to achieve bipolar operation. since any gain can be realized by choosing resistor values (r 1 +r 2 ), the v ref value must be selected first. if a v ref of 4.096v is used (g=2), solve for the amplifier?s gain by setting the dac to 0, knowing that the output needs to be -2.05v. the equation can be simplified to: 4. next, solve for r 3 and r 4 by setting the dac to 4096, knowing that the output needs to be +2.05v. mcp482x v dd v dd spi? 3 v out r 3 r 4 r 2 r 1 v in + g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) 0.1 f v cc + v cc ? v out 2.048 g d 2 12 ------- ? = v in+ v out r 4 r 3 r 4 + ------------------- - = v o v o v in+ 1 r 2 r 1 ----- - + ?? ?? v dd r 2 r 1 ----- - ?? ?? ? = r 2 ? r 1 -------- - 2.05 ? 4.096v ---------------- - = if r 1 = 20 k and r 2 = 10 k , the gain will be 0.5 r 2 r 1 ----- - 1 2 -- - = r 4 r 3 r 4 + () ----------------------- 2.05v 0.5 4.096v ? () + 1.5 4.096v ? ------------------------------------------------------ - 2 3 -- - == if r 4 = 20 k , then r 3 = 10 k
? 2005 microchip technology inc. ds21953a-page 23 MCP4821/mcp4822 6.7 selectable gain and offset bipolar voltage output using a dual dac in some applications, precision digital control of the output range is desirable. example 6-4 illustrates how to use the mcp482x family to achieve this in a bipolar or single-supply application. this circuit is typically used for linearizing a sensor whose slope and offset varies. the equation to design a bipolar ?window? dac would be utilized if r 3 , r 4 and r 5 are populated. example 6-4: bipolar voltage source with selectable gain and offset. mcp482x v dd r 3 r 4 r 2 v o mcp482x v dd r 1 dac a (gain adjust) dac b (offset adjust) spi? 3 r 5 v cc + thevenin bipolar ?window? dac using r 4 and r 5 g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) 0.1 f v cc ? av ss = gnd v cc + v cc ? v outb 2.048v g b ? () d b 2 12 ------- = v outa v outb v outa 2.048v g a ? () d a 2 12 ------- = v in+ v outb r 4 v cc- r 3 + r 3 r 4 + ----------------------------------------------- - = v o v in+ 1 r 2 r 1 ----- - + ?? ?? v outa r 2 r 1 ----- - ?? ?? ? = equivalent v 45 v cc+ r 4 v cc- r 5 + r 4 r 5 + ------------------------------------------- - = r 45 r 4 r 5 r 4 r 5 + ------------------ = v in+ v outb r 45 v 45 r 3 + r 3 r 45 + ----------------------------------------------- = v o v in+ 1 r 2 r 1 ----- - + ?? ?? v outa r 2 r 1 ----- - ?? ?? ? = offset adjust gain adjust offset adjust gain adjust
MCP4821/mcp4822 ds21953a-page 24 ? 2005 microchip technology inc. 6.8 designing a double-precision dac using a dual dac example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit dac. this design is simply a voltage divider with a buffered output. as an example, if a similar application to the one developed in section 6.6.1 ?design a bipolar dac using example 6-3? required a resolution of 1 v instead of 1 mv, and a range of 0v to 4.1v, then 12-bit resolution would not be adequate. 1. calculate the resolution needed: 4.1v/1 v = 4.1e06. since 2 22 = 4.2e06, 22-bit resolution is desired. since dnl = 0.75 lsb, this design can be attempted with the mcp482x family. 2. since dac b ?s v outb has a resolution of 1 mv, its output only needs to be ?pulled? 1/1000 to meet the 1 v target. dividing v outa by 1000 would allow the application to compensate for dac b ?s dnl error. 3. if r 2 is 100 , then r 1 needs to be 100 k . 4. the resulting transfer function is shown in the equation of example 6-5. example 6-5: simple, double-precision dac. mcp482x v dd r 2 v o mcp482x v dd r 1 dac a (fine adjust) dac b (course adjust) spi? 3 r 1 >> r 2 v o v outa r 2 v outb r 1 + r 1 r 2 + ----------------------------------------------------- = g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) 0.1 f v cc + v cc ? v outa 2.048v g a d a 2 12 ------- ? = v outb 2.048v g b d b 2 12 ------- ? = v outa v outb
? 2005 microchip technology inc. ds21953a-page 25 MCP4821/mcp4822 6.9 building a programmable current source example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the dac?s voltage output into a digitally-selectable current source. adding the resistor network from example 6-2 would be advantageous in this application. the smaller r sense is, the less power dissipated across it. however, this also reduces the resolution that the current can be controlled with. the voltage divider, or ?window?, dac configuration would allow the range to be reduced, thus increasing resolution around the range of interest. when working with very small sensor voltages, plan on eliminating the amplifier's offset error by storing the dac's setting under known sensor conditions. example 6-6: digitally-controlled current source. mcp482x r sense i b load i l v dd spi? 3 v cc + v cc ? v out g = gain select (1x or 2x) d = digital value of dac (0 ? 4096) i l v out r sense -------------- - 1 + ------------ = v out 2.048v g d 2 12 ------- ? = i b i l ---- =
MCP4821/mcp4822 ds21953a-page 26 ? 2005 microchip technology inc. 7.0 development support 7.1 evaluation & demonstration boards the mixed signal pictail ? demo board supports the mcp482x family of devices. refer to www.microchip.com for further information on this product?s capabilities and availability. 7.2 application notes application notes illustrating the performance and implementation of the mcp482x family are planned but are currently not released. refer to www.microchip.com for further information.
? 2005 microchip technology inc. ds21953a-page 27 MCP4821/mcp4822 8.0 packaging information 8.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn MCP4821 e/p ^ 256 0524 MCP4821e sn^^ 0524 256 8-lead msop example: xxxxxx ywwnnn 4821e 524256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e
MCP4821/mcp4822 ds21953a-page 28 ? 2005 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 5 5 - - dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (r e f e r e nc e ) e xc ee d .010" (0.254mm) p e r sid e . not e s: drawing no. c04-111 *controlling param e t e r mold draft angl e top mold draft angl e bottom foot angl e l e ad width l e ad thickn e ss c b .003 .009 .006 .012 dim e nsion limits ov e rall h e ight mold e d packag e thickn e ss mold e d packag e width ov e rall l e ngth foot l e ngth standoff ov e rall width numb e r of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equival e nt: mo-187 0 - 8 5 5 - - 15 15 - - - -
? 2005 microchip technology inc. ds21953a-page 29 MCP4821/mcp4822 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
MCP4821/mcp4822 ds21953a-page 30 ? 2005 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2005 microchip technology inc. ds21953a-page 31 MCP4821/4822 appendix a: revision history revision a (june 2005) ? original release of this document.
MCP4821/4822 ds21953a-page 32 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21953a-page 33 MCP4821/4822 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: MCP4821: 12-bit dac with spi? interface MCP4821t: 12-bit dac with spi interface (tape and reel) (soic, msop) mcp4822: 12-bit dac with spi interface mcp4822t: 12-bit dac with spi interface (tape and reel) (soic, msop) temperature range: e = -40c to +125c package: ms = plastic msop, 8-lead p = plastic dip (300 mil body), 8-lead sn = plastic soic, (150 mil body), 8-lead part no. x /xx package temperature range device examples: a) MCP4821t-e/sn: tape and reel extended temperature, 8ld soic package. b) MCP4821t-e/ms: tape and reel extended temperature, 8ld msop package. c) MCP4821-e/sn: extended temperature, 8ld soic package. d) MCP4821-e/ms: extended temperature, 8ld msop package. e) MCP4821-e/p: extended temperature, 8ld pdip package. a) mcp4822t-e/sn: tape and reel extended temperature, 8ld soic package. b) mcp4822-e/p: extended temperature, 8ld pdip package. c) mcp4822-e/sn: extended temperature, 8ld soic package.
MCP4821/4822 ds21953a-page 34 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21953a-page 35 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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